Description of the Conventional Art
A non-volatile memory device may electrically erase and program data, but may preserve stored data even without application of a supply voltage. An example, non-volatile memory device is a flash memory.
A memory cell may include a cell transistor having a control gate, a floating gate, a source and a drain. The cell transistor may be programmed or erased using a Fowler-Nordheim (F-N) tunneling mechanism.
An example erase operation of the cell transistor may be performed by applying a ground voltage to the control gate of the cell transistor and a voltage higher than a supply voltage to a semiconductor substrate (or a bulk). Under an erase bias condition, a relatively large voltage difference between the floating gate and the substrate may cause a relatively strong electric field there between. As a result, electrons in the floating gate may discharge to the substrate due to F-N tunneling. As a result, the threshold voltage of the erased cell transistor may decrease.
In an example, program operation, a voltage higher than the supply voltage may be applied to the control gate and a ground voltage may be applied to the drain, the source and the substrate. In a program bias condition, electrons may be injected to the floating gate of the cell transistor through F-N tunneling. As a result, a threshold voltage of the programmed cell transistor may increase.
FIG. 1 is a view for explaining the structure and operation of a memory cell included in a non-volatile memory device.
As illustrated in FIG. 1, electrons may be injected to the floating gate FG of the memory cell included in the non-volatile memory device. A state in which electrons may be injected to the floating gate FG is referred to as a “program state.” A state in which electrons may be erased from the floating gate FG is referred to as an “erase state.”
In the program state, a threshold voltage of the floating gate FG may be higher than about “0,” or positive. In the erase state, a threshold voltage of the floating gate FG may be lower than “0,” or negative.
To improve density of flash memories, a multi-level flash memory may be used. In a multi-level flash memory, a plurality of data bits (e.g., multi-bit data) may be stored in a single memory cell. For example, multi-bit data (e.g., two or more bits) may be stored in each memory cell. A memory cell storing multi-bit data is referred to as a “multi-level cell,” and a memory cell storing a single-bit data is referred to as a “single-level cell.” The multi-level cell may store multi-bit data utilizing two or more threshold voltages. Each of threshold voltages may be included in the corresponding threshold voltage distribution of a plurality of threshold voltages. A multi-level cell may also have two or more data storage states corresponding to the two or more threshold voltage distributions. An example in which 2 bits of data are stored in a memory cell of a multi-level flash memory will be described. However, three or more bits of data may be stored in a memory cell of the multi-level flash memory.
A multi-level cell storing 2 bit data may have four data storage states, for example, “11”, “01”, “10”, and “00”. In this example, “11” represents an erased state, and “01”, “10”, and “00” represent programmed states.
The four data storage states may correspond to respective threshold voltage distributions of the multi-level cell. For example, if the threshold voltage distributions of the multi-level cell are “VTH1-VTH2”, “VTH3-VTH4”, “VTH5-VTH6”, and “VTH7-VTH8”, the data storage states “11”, “01”, “10”, and “00” may correspond to voltage distributions “VTH1-VTH2”, “VTH3-VTH4”, “VTH5-VTH6”, and “VTH7-VTH8”, respectively. In this example, 2 bit data may be stored in the multi-level cell according to threshold voltages “11”, “01”, “10”, and “00”.
FIG. 2 is a view for explaining an example operation of a multi-level cell included in a non-volatile memory device.
FIG. 2 illustrates an erase state in which no electrons are in the floating gate FG of the multi-level cell, a first program state in which a first portion of electrons are injected to the floating gate FG of the multi-level cell, a second program state in which a second portion of electrons are injected to the floating gate FG of the multi-level cell, and a third program state in which a relatively large amount of electrons are injected to the floating gate FG of the multi-level cell. From the erase state to the third program state, threshold voltages may increase gradually.
FIG. 3 illustrates a plurality of threshold voltage distributions for the conventional multi-level cell illustrated in FIG. 2.
Referring to FIG. 3, 16 threshold voltage distributions of the conventional multi-level cell may represent 4-bit data. The 16 threshold voltage distributions may correspond to combinations of 4-bit codes.
Memory cell programming may be performed by changing a threshold voltage of a memory cell. Changing a threshold voltage of a programmed memory cell may generate a coupling effect in memory cells adjacent to the programmed memory cell, which may change threshold voltages of the adjacent memory cells. In this example, the larger the change of the threshold voltage when programming, the greater the coupling effect. In addition, a threshold voltage change at the latter half of programming may cause a greater coupling effect than a threshold voltage change at the beginning of programming.